In a computer system, a memory controller is mainly responsible for data exchanges between a CPU and a memory, and physical address management of the memory is implemented by an operating system. The operating system allocates a virtual address to a process. If a translation look-aside buffer (TLB) does not cache the virtual address, and a memory management unit (MMU) does not find a page table entry of the virtual address, a page fault occurs and the CPU is trapped in the kernel of the operating system. When the page fault occurs, the operating system enters an interrupt service routine, performs site protection, pushes various status information of a current instruction such as a program counter onto a stack, and checks validity of the virtual address. If determining that the access is invalid, the operating system usually feeds back a signal to the process or directly kills the process.
In the prior art, if the MMU does not find the page table entry of the virtual address, the MMU directly triggers a page fault, and causes the CPU to be trapped in the kernel of the operating system for a long time. When the page fault occurs, the operating system needs to perform a series of processing, which increases load on the operating system, and management efficiency is relatively low.